The Green Hills Optimizing Compilers for SH all utilize a common code generator with architecture-specific optimizations.
Each supported SH model has its own particular optimization and instruction set characteristics. In addition
for the SH-2A architecture, Green Hills offers CodeFactor®, a link-time optimization that reduces overall
program size by identifying and removing redundant segments of code from object files.
In certified EEMBC benchmarks, CodeFactor reduced code size an additional 10%. These are
accommodated in the code generator to produce code best suited for the target processor. The Green Hills SH Optimizing
Compilers support the following SH-specific features:
 | Processor - One option for each supported SH model. This setting determines the instructions permitted, as well as the pipeline optimization strategy used. |
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| Position Independent Code (PIC)- Allows executable files and data to be placed anywhere in memory and still run correctly. |
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| Little Endian - Causes programs to be compiled and assembled using a little-endian memory model (the default is big-endian). |
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| All Floating Point is single precision - This option will cause "double" to be interpreted as "float" so no 64-bit instructions will be required for floating point operations.
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| Disable use of MACH, MACL, and GBR by compiler - Prevents the compiler from using the MACH, MACL, or GBR registers as general purpose, permanent registers. |
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| Large switch statements - Allows large switch statements by forcing the compiler to use a 32-bit offset, which works regardless of the destination label. |
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| Small Data Area - The SH processor requires a literal pool entry to compute an arbitrary 32-bit address. The Green Hills compilers enable the user to collect frequently accessed variables into a block of memory, accessible via offsets from the GBR register, instead of requiring a pool entry thereby saving code size and improving performance.
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Source Level Support/Extensions for SH-DSP
C and C++ programmers can take advantage of the parallel memory access and fixed point instructions and registers provided by the SH-DSP by using the special DSP features supported by the Green Hills C/C++ compilers, including:
 X and Y Parallel Memory Access
Zero Overhead Loops
Fixed Point Data Type Class Support in C++
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| Run-Time libraries |
A comprehensive suite of run-time libraries for C, C++, and EC++ are included in the corresponding compiler distributions for each language. Several different versions of the libraries are provided to accommodate different combinations of processor and memory models. The combinations include hardware vs. software floating point, big endian vs. little endian memory models and CPU specific versions. Full featured start-up code and libraries include automatic copy of data from ROM to RAM and system call emulation. Source code to the run-time libraries is available so that users can customize routines according to the special needs of their applications.
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| The MULTI Integrated Development Environment |
MULTI provides a host-based (Windows 9x/NT/2000 PC or UNIX workstation) graphical environment
for SH target development. Host-target connectivity is provided through a variety of means, depending on the
target environment. MULTI supports a variety of SH evaluation boards from Hitachi including 7032, 7043, 7410,
7604, 7612, 7708, 7729, and 7750 boards. These boards can be accessed with a variety of interfaces:
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Bare Board Access (No RTOS or ROM Monitor) - MULTI supports Hitachi's E10A and E10 In-Circut Emulators through HDserv and HEserv, respectively. MULTI provides a complete software package that enables programmers to debug code without need for operating systems, kernels, or even ROM monitors. |
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ROM Monitor - MULTI supports SH targets running the GHSmon monitor. |
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Custom RTOS Support - MULTI can be interfaced with a custom RTOS through integration of the Green Hills INDRT API. INDRT provides all the debug information needed by MULTI, and is easily integrated into custom RTOS code. |
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Instruction Set Simulator - The SimSH instruction set simulator interpretively executes SH programs on the host PC or workstation without the need for target hardware by simulating the execution of the target processor at the instruction level. SimSH provides full debug features, host I/O, command window, extended profiling and hardware breakpoints. |
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* This feature is configuration-dependent and may require custom integration. Please contact your local sales representative for further information.
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