Leading the Embedded World

RISC-V

Embedded Software Solutions
RISC-V Embedded Software Solutions

Real-time operating systems

  • INTEGRITY RTOS
    For totally reliable and absolutely secure applications
  • µ-velOSity RTOS
    Small, fast, easy-to-learn operating system for the most cost-sensitive and resource-constrained devices

Software Development tools

Processor Probes

  • Green Hills Probe V4
    For multicore hardware bring-up, low-level debugging, and trace-powered analysis tools
RISC-V embedded development solution from Green Hills Software

The MULTI IDE and Green Hills C/C++ Optimizing Compilers and toolchain for RISC-V provide key features to the RISC-V architecture:

Partner Ecosystem

  • Andes Technology
  • Lattice Semicoductor
  • Microchip
  • NSI-TEXE
  • Renesas
  • SiFive

Architecture-specific support for RISC-V

The Green Hills C/C++ Optimizing Compilers for RISC-V bring the following key features to the RISC-V architecture:

  • Support for a comprehensive list of ISA modules
  • Both 32-bit and 64-bit RISC-V architectures are supported
  • Compiler and debugger support for custom Instructions
  • Decades of industry-leading experience in C/C++ compiler technology that generates the fastest, smallest, and most reliable code

RISC-V is a free, open, and extensible instruction set architecture based on reduced instruction set computer principles. RISC-V is modular in nature allowing designers to include only the instruction set modules that they require, and to incorporate their own custom instructions into their design.

The Green Hills compiler supports the modular nature of the RISC-V architecture by allowing the user to choose exactly the instruction set modules they would like to compiler their code for. Supported instruction set modules are:

32- and 64-bit: rv32i, rv64i
“A” Atomic instructions
“B” Bit manipulation
“C” Compressed instruction set
“F, D” Single and double precision floating point
“Q” Quad precision floating point in assembler/linker
“G” IMAFD Zicsr Zifencei
“H” Hardware hypervisor (in progress, 2023)
“I” Base integer unit
“M” Multiple and divide unit
“P” Packed SIMD instructions (in progress)
“V” Vector instructions in assembler/linker
“Zfinx” Single-precision FP in integer registers
“Zdinx” Double-precision FP in integer registers (Q3 2022)

Additionally, RISC-V includes a separate privileged instruction set specification. These privileged instructions are supported.

Pre-built runtime libraries are provided for compatibility with all of these configurations.

RISC-V Custom Instructions
A popular feature of the open RISC-V architecture is that users can incorporate their own custom instructions into their design. The Green Hills development tools offer an easy way to add new instructions into the compiler, assembler, MULTI debugger, and instruction set simulator.

For more information about Green Hills optimizing compilers for C and C++, click here.