Real-time operating systems
- µ-velOSity RTOS
Small, fast, easy-to-learn operating system for the most cost-sensitive and resource-constrained devices
Software Development tools
- MULTI development environments
Quickly develop, debug, test, and optimize embedded and real-time applications
- DoubleCheck integrated static analyzer
Easily pinpoint bugs early in development
- Green Hills Optimizing Compilers
Generating the smallest and fastest code from C and C++. See below for architecture-specific support for RISC-V.
- Green Hills Probe V4
For multicore hardware bring-up, low-level debugging, and trace-powered analysis tools
Customers today are using Green Hills embedded software development tools for RISC-V to achieve shorter development times, higher processor performance, and to gain competitive differentiation through the RISC-V’s custom instructions and modular instruction set architecture.
Architecture-specific support for RISC-V
The Green Hills C/C++ Optimizing Compilers for RISC-V bring the following key features to the RISC-V architecture:
- Support for a comprehensive list of ISA modules
- Both 32-bit and 64-bit RISC-V architectures are supported for all instruction set modules
- Compiler and debugger support for custom Instructions
- Decades of industry-leading experience in C/C++ compiler technology that generates the fastest, smallest, and most reliable code
RISC-V is a free, open, and extensible instruction set architecture based on reduced instruction set computer principles. RISC-V is modular in nature allowing designers to include only the instruction set modules that they require, and to incorporate their own custom instructions into their design.
The Green Hills compiler supports the modular nature of the RISC-V architecture by allowing the user to choose exactly the instruction set modules they would like to compiler their code for. Supported instruction set modules are:
- "I" Core integer set of instructions
- "A" Atomic instructions
- "M" Multiply and divide instructions
- "C" Compressed Instructions
- "F" Single precision floating point instructions
- "D" Double precision floating point instructions
- "G" Shorthand for “IMAFD"
Additionally, RISC-V includes a separate privileged instruction set specification. These privileged instructions are supported.
Pre-built runtime libraries are provided for compatibility with all of these configurations.
RISC-V Custom Instructions
A popular feature of the open RISC-V architecture is that users can incorporate their own custom instructions into their design. The Green Hills compilers offer an easy-to-learn and use interface for adding new instructions into the compiler, assembler, MULTI debugger, and instruction set simulator.