ARC Embedded Software Solutions

Software Development tools
  • MULTI development environments
    Quickly develop, debug, test, and optimize embedded and real-time applications
  • ARC MetaWare C/C++ Compiler
    Highly optimized and robust

Processor Probes
ARC MetaWare Compiler
The MULTI Integrated Development Environment for theARC processor includes the ARC MetaWare C/C++compiler. ARC's MetaWare compiler is highly optimizedand robust. Some of the most notable features include:

  • Intrinsics for users to define their own instruction
  • Intrinsics for core and auxiliary register access
  • Numerous optimizations amed at smaller and fastercode, including zero-delay loops, conditional instruc-tions, delay-slot filling, loop unrolling, common sub-expression elimination, instruction scheduling, etc.
  • Big and little endian addressing mode
  • Small-data area
  • Run-time library source code
  • Extensive linker command language for the control oftext and data placement
  • Compiler support for interrupt handling
  • Enhanced inline assembly

Run-Time Libraries

A complete implementation of C libraries is included incompiler distributions. In addition, C++ iostream librariesare provided. Full featured start-up code and librariesinclude automatic copy of data from ROM to RAM andsystem call emulation.

The MULTI Integrated Development Environment
MULTI provides a host-based (Windows® or Linux™ workstation) graphical environment for ARC target development. Host-target connectivity is provided througha variety of means, depending on the target environment. MULTI supports hardware connectivity, including theARCangelâ„¢evaluation board. These targets can be accessed through the following interfaces:

  • Bare Board Access (no RTOS or ROM Monitor): MULTI supports targets connected through JTAG head-ers on the board. ARC boards are supported with theGreen Hills Probe and the MetaWare SeeCode interface.
  • Instruction Set Simulator: The ARCserv debug serveris a utility that connects to the MetaWare InstructionSet Simulator (ISS). The simulator interpretively executesARC programs on the host PC or workstation withoutthe need for target hardware. In addition, developerscan extend the simulator with their own extensioninstructions, core registers, auxiliary registers, and con-dition codes to create a completely customized modelof their own processor. ARCserv can be configured tosimulate instruction and data caches, which can beviewed graphically in MULTI. The simulator keeps trackof count information for each instruction, whichincludes things like:
    • Instruction hit counts
    • Cycle count
    • Killed cycles due to branches
    • Stall cycles
    • Function entry counts