Embedded Avionics: Sponsored

Avionics Multicore Processors Require
Multicore Interference Mitigation

By Richard Jaenicke | September 15, 2020

Avionics, CAST-32A, Green Hills Software, safety-critical, real-time operating systems

The CAST-32A position paper defines 10 objectives to address the use of multicore processors in software airborn systems. The INTEGRITY-178 tuMP RTOS contains DAL-A mechanisms to enable system integrators to mitigate multicore interference.

Avionics systems that use multicore processors can see worst-case execution times (WCET) increase by 8-13x versus a single-core implementation. But a solution exists today to help system integrators mitigate the multicore interference that causes such increases in WCET.

Multicore interference occurs when one or more processor cores attempt to access a shared resource that is already in use by another core. The resulting delays can impact determinism, performance, and ultimately safety. A major congestion point is access to shared memory, but I/O, DMA, shared cache, and even the on-chip interconnect can also cause interference.

Although some mitigation can be done at the system level, such as carefully scheduling applications that don't access memory at the same time, those techniques have limited effectiveness and often break when any application is modified or replaced. That can cause costly retesting and verification of all applications.

A more general solution can be implemented at the operating system (OS) level in the same way that the OS accesses the hardware memory management unit (MMU) to provide memory space partitioning. By controlling access to the shared resources and limiting the bandwidth on a per-core basis, the OS can mitigate multicore interference. The INTEGRITY-178 tuMP RTOS implements that technique using DAL-A mechanisms to deliver predictable WCETs that are as much as 8x lower in the presence of multicore interference.

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