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ThreadX for SH Thread RTOS
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Express Logic's ThreadX® Real-Time Operating System (RTOS) is available from and supported by Green Hills Software. ThreadX is fully integrated with the Green Hills Software MULTI® Integrated Development Environment, providing Optimizing Compilers, Source Debugger, Graphical Project Builder and many other powerful tools for development of embedded application.

 
SH Family Supported

SH1
SH2
SH3
SH4
SH3-DSP

 

Supported IDE

MULTI For ThreadX



 
 
Highlights
Reasonable pricing
Royalty-Free
Complete ANSI C source code
Easy to use and powerful services
Responsive Technical Support
Unlimited Threads, Queues, Event Flags, Timers, Semaphores, Block Pools, and Byte Pools
Flexible memory usage
Timeout available on all thread suspension
Advanced preemption-threshold technology
Low-overhead Application Timers
Size scales automatically
picokernel architecture for size and speed
Small footprint (sizes in bytes):
     Instruction area size 3-20K
     Global data area 696
     Thread control block 144
     Queue control block 44
     Event Flag control block 28
     Timer control block 56
     Semaphore control block 32
     Block Memory control block 48
     Byte Memory control block 52


Fast Execution
(20MHz, 0 wait-states, SH3):
    context switch 6.8us
   tx_thread_suspend 14.6us
   tx_thread_resume 11.6us
   tx_thread_relinquish 4.8us
   tx_semaphore_get 4.6us
   tx_semaphore_put 4.6us
   tx_queue_send 7.6us
   tx_queue_receive 7.6us
   tx_event_flags_set 6.4us
   tx_event_flags_get 7.0us
   tx_block_allocate 5.6us
   tx_block_release 5.2us
   tx_byte_allocate 6.4us
   tx_byte_release 7.8us

SH Optimizations
ThreadX optimizes context switching on the Hitachi SH. When context switching occurs inside of a ThreadX service call, only the registers preserved across function calls are saved as part of the thread's context, i.e. registers R8-R14, PR, MACH, and MACL.

A similar technique is used in interrupt handling. On the front end of interrupt service routines, only the compiler's scratch registers are saved initially (registers R0-R7). The full register set is saved only if thread preemption is required.
 

Further Optimizations for the SH3
ThreadX is further optimized for the SH3. Register Bank 1 (BANK1) is used on the front-end of interrupt context saving for improved performance. When initial context saving is done, Register Bank 0 is available for use - including nested interrupts.
 
Improve Your Embedded Development

Let our extensive experience with Hitachi's SH family of microprocessors help your product development. The ThreadX high-performance real-time kernel, helps improve your product's quality and its time-to-market. In addition, using ThreadX makes it easier to enhance your product in the future.


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