MULTI provides a host-based (Windows, Solaris, HP-UX and Linux) graphical environment for MIPS target development. Host-target connectivity is provided through a variety of means, depending on the target environment. MULTI supports many MIPS-based evaluation boards which can be accessed through a variety of interfaces:
Bare Board Access (No RTOS or ROM Monitor) - MULTI supports on-chip debugging through JTAG (EJTAG) hardware through the MDI (MIPS Debug Interface) protocol. MIPS-based boards from MIPS Technologies, IDT, NEC, Philips, Toshiba, Broadcom, Intrinsity, LSI Logic and others are supported by the Green Hills Probe™, EPI MAJIC™, Macraigor OCD, Agilent Emulation Probe and First Silicon Solutions probe.
ROM Monitor - Monitors—MULTI supports a variety of boards with PMON and IDTsim.
Commercial RTOS Support - MULTI supports MIPS boards running Green Hills Software’s royalty-free µ-velosity and velOSity RTOS and the INTEGRITY RTOS, ThreadX from Express Logic, and Tornado/VxWorks from Wind River Systems. MULTI provides multitask-aware debugging, and special commands that allow tasks to be stopped upon system events such as task creation.
Run-Mode Debugging - Run-Mode enables source debugging of one or more threads of execution within their own colored debug window, allowing the rest of the system to continue to run, handling real-time events. This advanced feature adds very little overhead to the embedded program making it ideal for deeply embedded real-time applications.
Custom RTOS Support - MULTI can be interfaced with a custom RTOS through integration of the Green Hills INDRT API.
Instruction Set Simulators (ISS) -MULTI is tightlyintegrated with Instruction Set Simulators to providecomplete debug capabilities that would be availablewith a hardware target: host I/O, command windows,extended profiling and hardware breakpoints. Thisenables users to prototype embedded applications earlyin the development cycle when silicon is unavailable.The Simmips ISS simulates the execution of the targetprocessor at the instruction level. The MIPSsim™ ISSfrom MIPS Technologies is available as an InstructionAccurate or Cycle Accurate model. Both Simmips and MIPSsim simulate target CPU cache for those processorswhich support it.
