 | Processor Options - One option for each supported model. This setting determines the instructions permitted. |
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| Position Independent Code (PIC) and Data (PID) - Allows code and
data to be created which can be placed anywhere in memory and still run correctly. |
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| MIPS Assembler Compatible Output - Generate assembly language output which is compatible with native MIPS assemblers from MIPS-based workstations from Silicon Graphics and other companies. |
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| Far Function Calls - Handles code that exceeds the limits of the call instruction. |
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| Inline Prologue - Generates inlined code or calls a routine when saving and restoring registers. |
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| Small Data Area - The Green Hills Compilers collect frequently accessed variables into a block of up to 64KB of memory. This enables single instruction access to data within this block, saving code size and improving performance. |
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| FastMATH Matrix Engine Instructions - Every FastMATH processor matrix instruction is supported through a compiler intrinsic, providing efficient access from C/C++. In addition, all assembly level matrix operations are supported, including Memory Access, ALU, Logical, Comparison, Multiply/Accumulate, Inter-Element Movement, and Inter-Element Computation. |
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| FastMIPS and FastMATH Processor Pipeline - The compiler and tool chain have been optimized for FastMATH and FastMIPS processors' 12-stage dual-issue pipeline. The pipeline optimizer will re-order both MIPS core and Matrix Engine instructions, based on latency and subject to data dependency constraints. |
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| 64-bit Integers - Supports 64-bit data types, constants, and expressions for all Intrinsity processors. |
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| FastMATH Matrix Registers - The compiler will automatically allocate matrix types to both the FastMATH matrix registers and accumulator registers.
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| Run-Time libraries |
| A complete implementation of the C, C++, and EC++ libraries are included in all compiler distributions. Full featured start-up code and libraries include automatic copy of data from ROM to RAM and system call emulation. Source code to the run-time libraries is available so that users can customize routines according to the special needs of their applications. |
| The MULTI Integrated Development Environment |
| MULTI provides a host-based (Windows 9x/NT/2000/ME/XP PC or UNIX workstation) graphical environment for Intrinsity target development. The MULTI debugger provides full visibility into all Matrix Engine registers, as well as all GP registers. This enables developers to debug matrix routines written in C, using compiler intrinsics, or in assembly language. |
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Bare Board Access (No RTOS or ROM Monitor) - MULTI supports on-chip debugging through JTAG (EJTAG) hardware through the MDI (MIPS Debug Interface) protocol. FastMATH and FastMIPS processor-based boards are supported by the Green Hills Probe™. |
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ROM Monitors - MULTI supports YAMON™, PMON and IDTsim monitors. |
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INTEGRITY Support - a port to the FastMATH and FastMIPS processors and an evaluation board is scheduled to be completed soon after evaluation hardware is available. |
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Custom RTOS Support - MULTI can be integrated with a custom RTOS through the Green Hills INDRT API. INDRT provides all the debug information needed by MULTI, and is easily integrated into custom kernel code. |
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Instruction Set Simulator - Instruction Set Simulators are used as host based software replacements for target hardware. MULTI is tightly integrated with the simulators, providing the same full debug features that would be available with a hardware target: host I/O, command window, extended profiling and hardware breakpoints. The simint ISS, is intended for use with FastMIPS and FastMATH cores from Intrinsity, and is Cycle Accurate (CA). |
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